1 of 2 october 26, 2009 ? 2009 integrated device technology, inc. idt and the idt logo are regi stered trademarks of integr ated device technology, inc. ? device overview the idt qspan ii is a pci-to-host processor bridge for the freescale powerquicc (mpc860/850/821), the quicc (mc68360), and the mc68040. it has a growing customer list of tier-one communications vendors. the qspan ii operates at speeds up to 50 mhz on the host processor bus, with programmable parity and bur st/prefetch capability. its 32-bit/ 33 mhz pci 2.2 support is ideal for embedded processor applications. another key feature of the qspan ii is its integrated pci bus arbiter. this arbiter supports up to seven exter nal bus masters and uses a fairness algorithm to prevent deadlocks on the bus. block diagram the qspan ii also has a dma controller for reliable, high-performance data transfer between the pci bus and the host processor bus. two modes of dma operation (direct and linked list) offer designers a greater level of flexibility. the qspan ii further distinguis hes itself by providing embedded systems designers access to compac tpci hot swap, pci v2.2 vital product data (vpd), power managemen t, and four, 32-bit mailbox regis- ters. the device is offered in two packages: a 17 x 17 mm package with a 1.0 mm ball pitch, and a 27 x 27 mm package with a 1.27 mm ball pitch. 32-bit address and data 50 mhz processor bus 32-bit address and data 33 mhz pci bus hot swap controller i 2 0 hot swap friendly four fifo messaging ieee1149.1 boundary scan up to 7 external bus masters jtag pci bus arbiter 8091862_bk001_03 qbus slave channel posted writes, prefetched reads, delayed single reads/writes pci target channel posted writes, prefetched reads, delayed single reads/writes interrupt channel pci/qbus interrupts, mailbox registers idma/dma channel fifo-based, direct/linked list mode qbus (processor) interface pci interface features ? integrated pci bus arbiter ? supports up to seven external bus masters ? fairness algorithm fo r preventing deadlocks ? compactpci hot swap friendly ? high-performance dma controll er with support for direct and linked list modes ? mailbox registers for passi ng parameters between host and embedded environments ? pci version 2.2 enhancements ? vital product data: offers an improved method of communi- cating board-specific information to the system ? pci power management interface: enables operating systems to control the power supplied to qspan ii related hardware (for example, an add-in card) ? high-performance pci bus interface ? zero-wait state bursts, prefetch reads and writes on pci ? serial eeprom interface for plug and play compatibility on pci ? universal pci signaling (3.3 and 5v compliant) ? high-performance processor interface ? mpc860 interface supports pref etched reads and burst writes ? operates up to 50 mhz benefits ? industry-proven pci syst em interconnect device ? reduces customer?s design hour s and time-to-market using qspan ii?s design support tools typical applications qspan ii?s typical applications include the following: ? lan/wan infrastructure ? network interface cards ? routers (including soho applications) ? servers ? remote and local access equipment ? xdsl concentrators ? voip gateways ? cpe equipment ? process control equipment ? data acquisition systems qspan ii ? powerquicc-to-pci bridge product brief
qspan ii product brief 2 of 2 october 26, 2009 august 16, 2004august 16, 200 not an offer for sale the information presented herein is subjec t to a non-disclosure agreement and is fo r planning purposes only. nothing contained in this presenta- tion, whether verbal or written, is int ended as, or shall have the effect of, a sale or an offer for sale that creates a contra ctual power of acceptance. corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: ehbhelp@idt.com phone: 408-360-1538 document: 8091862_md900_09 ? ? other ? pmc cards ? set-top boxes ? any 68k-based or powerpc-based system migrating to the pci bus the following diagram shows a qs pan ii router application. in this example, one qspan ii is used as a s ystem host bridge and the other is used on a peripheral adapter card. router application controller card i/o card i/o card i/o card pci bus 8091862_ta001_02 processor bus processor bus ethernet, ti/e1, etc. memory qspan ii memory qspan ii mpc860 mpc860
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